The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to a semiconductor device having a bipolar integrated circuit with I.sup.2 L elements and a method for manufacturing the same.
An I.sup.2 L (Integrated Injection Logic) is a logic element which has a composite structure involving a vertical transistor (e.g., an npn transistor) of inverted structure and a lateral transistor (e.g., a pnp transistor) of complementary structure to that of the vertical transistor. In an I.sup.2 L element of the structure as described above, the lateral transistor serves as an injector for injecting charge into the base of the vertical transistor which, in turn, serves as an inverter. For this reason, I.sup.2 L elements have a small logic amplitude and are capable of operating at high speed with low power consumption. Since element isolation between the vertical and lateral transistors is unnecessary, I.sup.2 L elements can achieve a high integration and are suitable for large scale integration. Furthermore, since an I.sup.2 L involves the bipolar process technique, other bipolar circuits such as linear and ECL (Emitter Coupled Logic) circuits may be easily formed on the same chip, thus realizing a multi-functional integrated circuit.
Various studies have been made to achieve higher operation speed of the I.sup.2 L. It has been recently pointed out that it is important to achieve a short storing time, that is, the time required for a switching transistor to sink the minority carriers stored at an emitter or base region of a switching transistor of the next stage. This is described, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-14. No. 2, April 1979, pp. 327 to 336. In order to eliminate storage of minority carriers, it is effective to optimize the concentration profile of the epitaxial semiconductor layer and the emitter region as well as to minimize the size of the region at which the minority carriers are stored. In view of this, it has been conventionally proposed to manufacture I.sup.2 L elements by the method to be described below. According to this conventional method, referring to FIGS. 1A to 1C, an n.sup.+ -type buried layer 2 is selectively formed in a p-type silicon substrate 1. After growing an n-type epitaxial layer 3 on the substrate 1, a thick field oxide film 4 for element isolation is formed by selective oxidation. After selectively forming a silicon oxide film 5 on the prospective element forming region by the CVD process or photolithography, boron is thermally diffused through the silicon oxide film 5 as a mask to form a p-type base region 6 and a p-type injector 7 (FIG. 1A). In the next step, an arsenic-doped polycrystalline silicon film (arsenic is an n-type impurity) is deposited over the entire surface of the structure. The arsenic-doped polycrystalline silicon film is selectively etched to form n.sup.+ -type polycrystalline silicon patterns 8a and 8b on collector forming regions (FIG. 1B). Thermal oxidation under heating is performed to grow a thick thermal oxide film 9 around the polycrystalline patterns 8a and 8b and to grow a thin thermal oxide film 10 on the p-type injector 7. Arsenic doped in the polycrystalline silicon patterns 8a and 8b is diffused into the p-type base region 6 to form n.sup.+ -type collector regions 11a and 11b. The thin thermal oxide film 10 is etched to provide the polycrystalline silicon patterns 8a and 8b as collector electrodes 12a and 12b. After an aluminum film is deposited over the entire surface of the structure, the aluminum film on the field oxide film 4 and the silicon oxide film 5 is patterned to form a base electrode 13 and an injector electrode 14. An integrated circuit including an I.sup.2 L element is thus completed (FIG. 1C). Referring to FIGS. 1A to 1C, reference numerals 15a to 15c denote base contact holes, and reference numeral 16 denotes an injector contact hole.
In the conventional method for manufacturing an integrated circuit with an I.sup.2 L described above, the entire surface of the substrate is oxidized utilizing differences between etching rates of the n.sup.+ -type polycrystalline silicon patterns 8a and 8b and of the p-type base region 6 at a low temperature. Thereafter, only a thin portion above the p-type base region 6 can be etched. The base contact holes can be formed in self-alignment with the collector electrodes 12a and 12b, so that the base electrode 13 may be able to contact the base region 6 with a wider area. Moreover, the area of the base region 6 may be made smaller than the total area of the collector regions 11a and 11b. An I.sup.2 L element manufactured is capable of high speed operation, and the ratio of the collector area to the base area (S.sub.C /S.sub.B) is increased. Therefore, the current amplification factor (h.sub.FE) can be improved and higher integration can also be achieved. However, in the above I.sup.2 L arrangement, the collector regions 11a and 11b and the base contact holes 15a and 15b come close to each other when the oxide film is etched too much, resulting in flow of a leakage current therebetween.
The following problems are presented in the elaborate patterning of the I.sup.2 L structure. The n.sup.+ -type polycrystalline silicon layer which is patterned as the n.sup.+ -type polycrystalline silicon layers 8a and 8b and the p-type base region 6 contact each other. In order to selectively etch the n.sup.+ -type polycrystalline silicon layer, the etching rates of the n.sup.+ -type polycrystalline silicon layer and the p-type base region 6 are controlled so that the p-type base region 6 may not be etched when it is exposed after the n.sup.+ -type polycrystalline silicon layer is selectively etched. In order to achieve selective etching of this type, an etchant of HF:HNO.sub.3 :CH.sub.3 COOH=1:3:8 is known. The etching rate of the n.sup.+ -type polycrystalline silicon layer is at least ten times that of the p-type base region 6. However, the etchant of this type is not suitable for elaborate etching. If a pattern width of the n.sup.+ -type polycrystalline silicon layer is 1 to 2 .mu.m and if the etchant described above is used, the side surfaces of the n.sup.+ -type polycrystalline silicon layer are etched by isotropic etching. Therefore, it is difficult to control precision of the n.sup.+ -type polycrystalline silicon pattern. It is also difficult to maintain the etching rate constant on the entire surface of the wafer. Thus, elaborate patterning is limited. Meanwhile, a reactive ion etching (RIE) method is known in which patterning of 1 to 2 .mu.m is effectively performed by anisotropic etching. However, at present, there is no RIE method which allows selective etching of the n.sup.+ -type polycrystalline silicon layer and the p-type region. If the conventional RIE method is used to etch the n.sup.+ -type polycrystalline silicon layer, the p-type base region is also etched. This method is not suitable for achieving the I.sup.2 L arrangement shown in FIG. 1C.